TickTick-Pao

Intel dumps ‘tick-tock’ development strategy

 

tick-tock history

Intel’s long used ‘tick-tock’ product development strategy is now no more. The chip maker introduced this method ten years ago to have a predictable introduction for new manufacturing techniques on existing processor design (tick) and introducing new architectures (tock). Meaning every tick introduced optimised power consumption and newer SKUs with variable clock speeds with existing design and every tock introduced more features and better performance on the newer architecture.

As an example, Intel Broadwell is ‘tick’ strategy and ‘tock’ represented Skylake.

This was to ensure that the new CPU architecture doesn’t come at the same time as the new process node. But now, it will be replaced with another strategy- Processor, Architecture and Optimization (PAO)?

TickTick-Pao

Intel mentioned the following in its 10-K filing:

As part of our R&D efforts, we plan to introduce a new Intel Core microarchitecture for desktops, notebooks (including Ultrabook devices and 2 in 1 systems), and Intel Xeon processors on a regular cadence. We expect to lengthen the amount of time we will utilize our 14nm and our next generation 10nm process technologies, further optimizing our products and process technologies while meeting the yearly market cadence for product introductions.

Intel also said that it will introduce its 14nm base Kaby Lake. At the same time, they are working to develop 10 nm manufacturing process.
The main issue Intel had with its Tick-Tock strategy is that it made it long to roll out new processor lineups. Broadwell was initially delayed in 2013 which was slated then for September 2014. Intel was also not able to release the complete SKU lineups it initially planned. By the time Intel released its mobile counterparts, it was time for Skylake to hit the market.

It seems that Intel is more keen on keeping the Moore’s Law up and running. The company said:

We have continued expanding on the advances anticipated by Moore’s Law by bringing new capabilities into silicon and producing new products optimized for a wider variety of applications. We expect these advances will result in a significant reduction in transistor leakage, lower active power, and an increase in transistor density to enable more smaller form factors, such as powerful, feature-rich phones and tablets with a longer battery life.

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