The JEDEC Solid State Technology Association which sets the DDR memory standard published a new document detailing the upcoming DDR5. The upcoming memory standard is typically used for computers varying from a low end, gaming systems all the way to servers. While the obvious benefits and improvements affect a wide range of users, this one addresses certain improvements for cloud computing and the enterprise market.
The new DDR5 memory standard brings efficient performance standards. Therefore it addresses higher scaling performance without reducing channel efficiency. It is able to be achieved by doubling up the memory’s burst length to BL16 and increase bank count to 32. As a result, the DDR5 modules will have 2x 40-bit independent sub-channels to provide that efficiency and reliability.
Major PC chipset and memory maker involved in the transition process
This is made possible will all the major players involved- AMD and Intel who makes processors for every use, followed by Samsung Electronics, Micron and SK Hynix that makes memory chips and sells to respective memory vendors like Kingston/HyperX and G SKill. Micron has its own retail branding where it sells RAMs and SSDs- Crucial, with Ballistix being its gaming sub-brand. Samsung also sells rams under its own name. Naturally, all will be involved (and many more) to help transition from current generation DDR4 to DDR5.
Even Micron published a whitepaper on DDR5, calling it as a ‘more than a generational upgrade‘.
AMD and Intel’s plans for DDR5 (so far)
It is likely to see Intel’s Alder Lake use DDR5 platform since it is scheduled for next year, with Rocket Lake to be out before 2020 ends. There’s really nothing known about AMD’s plans. But it is safe to say that Ryzen 4000 series CPUs are going to be for DDR4 since its scheduled to be out before the end of this year. By then, AMD might be having a new socket, just like how it said when it talked about Ryzen 1st gen platforms. Intel will also shift to LGA 1700, with LGA 1200 being a socket of choice for Comet Lake and Rocket Lake mainstream CPUs.
Upcoming DDR5 Standard
JEDEC said that the upcoming DDR5 standards are fine-tuned to allow an increase in performance and frequency without reducing channel efficiency. This is usually seen when memory frequency is increased while the timings increases, showing higher latency. The association is keen on making that a thing of the past. According to the documentation, it will double up the memory’s burst length to BL16 and increase its bank count from 16 to 32. Therefore the end product will have 2x 40-bit independent sub-channels. Micron has showcased its DDR5 rendering to give an idea.
Apart from performance and reliability increase, the new DDR5 standard brings in newer features. It will introduce Decision Feedback Equalization (DFE), I/O speed scalability and increased bandwidth to 4.8 Gbps, which is higher than DDR4’s End-of-Life speed at 3.2 Gbps. The DDR5 will also include a new feature called Decision Feedback Equalization, I/O speed scalability an and an increased bandwidth starting from 4.8 Gbps. DDR4 has End-of-Life speed up to 3.2 Gbps.
Specification and features
JEDEC DDR Standard Comparison
|Max Die Density||64 Gbit||16 Gbit|
|Max UDIMM Size||128 GB||32 GB|
|Max Data Rate||6.4 Gbps||3.2 Gbps|
|Width (Non-ECC)||64-bits (2×32)||64-bits|
|Banks (Per Group)||4||4|
DDR5 essentially doubles up everything about DDR4 and is able to lower the voltage. Looks like JEDEC is very serious about the upcoming specification to meet the high demand of enterprise and cloud computing.
The other DDR5 features are easier to follow-up:
- Fine-grain refresh feature: as compared to DDR4 all bank refresh improves 16 Gbps device latency. Same bank self-refresh offers better performance by enabling some banks to refresh while others are in use.
- On-die ECC and other scaling features enable manufacturing on advanced process nodes.
- Improved power efficiency enabled by Vdd going from 1.2 V to 1.1 V as compared to DDR4.
- Use of the MIPIÒ Alliance I3C Basic specification for system management bus.
- At the module level, the voltage regulator on DIMM design enables pay as you go scalability, better voltage tolerance for improved DRAM yields and the potential to further reduce power consumption.
The key change here is the on-DIMM voltage regulator. Usually, motherboard makers have voltage regulators for its DIMM slots. The DDR5 standard offloads that responsibility. It is extremely unlikely to result in this lower motherboard cost, but it would result in higher DDR5 cost.